Global NX

The STM32F051C8T6 is a microcontroller from STMicroelectronics, part of the STM32 family based on the ARM Cortex-M0 core. It is designed for low-power, cost-sensitive applications that require basic processing power and peripheral integration.

The MC6850P Asynchronous Communications Interface Adapter provides the data formatting and control to interface serial asynchronous data communications information to bus organized systems such as the MC6800 Microprocessing Unit.

• C Compiler Optimized Architecture
• Only 49 Instructions
• Operating Speed: - DC – 20 MHz clock input - DC – 200 ns instruction cycle
• Interrupt Capability with Automatic Context Saving
• 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset
• Direct, Indirect and Relative Addressing modes: - Two full 16-bit File Select Registers (FSRs) - FSRs can read program and data memory.

• C Compiler Optimized Architecture
• Only 49 Instructions
• Operating Speed: - DC – 20 MHz clock input - DC – 200 ns instruction cycle
• Interrupt Capability with Automatic Context Saving
• 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset
• Direct, Indirect and Relative Addressing modes: - Two full 16-bit File Select Registers (FSRs) - FSRs can read program and data memory.

• C Compiler Optimized Architecture
• 256 bytes Data EEPROM
• Up to 14 Kbytes Linear Program Memory Addressing
• Up to 1024 bytes Linear Data Memory Addressing
• Interrupt Capability with Automatic Context Saving
• 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset
• Direct, Indirect and Relative Addressing modes: - Two full 16-bit File Select Registers (FSRs) - FSRs can read program and data memory.

• Power-Saving Sleep mode
• Wide Operating Voltage Range (2.0V-5.5V)
• Industrial and Extended Temperature Range
• Power-on Reset (POR)
• Power-up Timer (PWRTE) and Oscillator Start-up Timer (OST)
• Brown-out Reset (BOR) with Software Control Option
• Enhanced Low-Current Watchdog Timer (WDT) with On-Chip Oscillator (Software selectable nominal 268 Seconds with Full Prescaler) with Software Enable
• Multiplexed Master Clear/Input Pin
• Programmable Code Protection.

• Only 35 Instructions to Learn: - All single-cycle instructions except branches
• Operating Speed: - DC – 20 MHz oscillator/clock input - DC – 200 ns instruction cycle
• Interrupt Capability
• 8-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes.

• 100,000 erase/write cycle Enhanced Flash program memory typical
• 1,000,000 erase/write cycle Data EEPROM memory typical
• Flash/Data EEPROM Retention: > 40 years
• Self-programmable under software control
• Priority levels for interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT): - Programmable period from 41 ms to 131s - 2% stability over VDD and Temperature
• Single-supply 5V In-Circuit Serial Programming™ (ICSP™) via two pins
• In-Circuit Debug (ICD) via two pins
• Wide operating voltage range: 2.0V to 5.5V.

• C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code
• Up to 1024 Bytes Data EEPROM
• Up to 64 Kbytes Linear Program Memory Addressing
• Up to 3896 Bytes Linear Data Memory Addressing
• Up to 16 MIPS Operation
• 16-bit Wide Instructions, 8-bit Wide Data Path
• Priority Levels for Interrupts
• 31-Level, Software Accessible Hardware Stack
• 8 x 8 Single-Cycle Hardware Multiplie.

• Operating Voltage Range: 2.0V to 3.6V
• 5.5V Tolerant Input (digital pins only)
• On-Chip 2.5V Regulator
• 4x Phase Lock Loop (PLL) available for Crystal and Internal Oscillators
• Self-Programmable under Software Control
• Low-Power, High-Speed CMOS Flash Technology
• C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT): - Programmable period from 4 ms to 131s
• Single-Supply In-Circuit Serial Programming™ (ICSP™) via Two Pins
• In-Circuit Debug (ICD) with Three Breakpoints via Two Pins.

• Run: CPU on, Peripherals on
• Idle: CPU off, Peripherals on
• Sleep: CPU off, Peripherals off
• Ultra Low 50nA Input Leakage
• Run mode Currents Down to 11 μA Typical
• Idle mode Currents Down to 2.5 μA Typical
• Sleep mode Current Down to 100 nA Typical
• Timer1 Oscillator: 900 nA, 32 kHz, 2V
• Watchdog Timer: 1.4 μA, 2V Typical
• Two-Speed Oscillator Start-up.

• Run: CPU on, Peripherals on
• Idle: CPU off, Peripherals on
• Sleep: CPU off, Peripherals off
• Ultra Low 50nA Input Leakage
• Run mode Currents Down to 11 A Typical
• Idle mode Currents Down to 2.5 A Typical
• Sleep mode Current Down to 100 nA Typical
• Timer1 Oscillator: 900 nA, 32 kHz, 2V
• Watchdog Timer: 1.4 A, 2V Typical
• Two-Speed Oscillator Start-up.

• C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code
• Up to 1024 bytes Data EEPROM
• Up to 64 Kbytes Linear Program Memory Addressing
• Up to 3936 bytes Linear Data Memory Addressing
• Up to 16 MIPS Operation
• 16-bit Wide Instructions, 8-bit Wide Data Path
• Priority Levels for Interrupts
• 31-Level, Software Accessible Hardware Stack
• 8 x 8 Single-Cycle Hardware Multiplier.

• C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code
• Up to 1024 Bytes Data EEPROM
• Up to 64 Kbytes Linear Program Memory Addressing
• Up to 3896 Bytes Linear Data Memory Addressing
• Up to 16 MIPS Operation
• 16-bit Wide Instructions, 8-bit Wide Data Path
• Priority Levels for Interrupts
• 31-Level, Software Accessible Hardware Stack
• 8 x 8 Single-Cycle Hardware Multiplier

• C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code
• Up to 1024 Bytes Data EEPROM
• Up to 64 Kbytes Linear Program Memory Addressing
• Up to 3896 Bytes Linear Data Memory Addressing
• Up to 16 MIPS Operation
• 16-bit Wide Instructions, 8-bit Wide Data Path
• Priority Levels for Interrupts
• 31-Level, Software Accessible Hardware Stack
• 8 x 8 Single-Cycle Hardware Multiplier.

• High current sink/source 25 mA/25 mA
• Four external interrupt pins
• Timer0 module: 8-bit/16-bit timer/counter
• Timer1 module: 16-bit timer/counter
• Timer2 module: 8-bit timer/counter
• Timer3 module: 16-bit timer/counter
• Timer4 module: 8-bit timer/counter
• Secondary oscillator clock option – Timer1/Timer3.

• Operating Voltage Range: 2.0V to 3.6V
• 5.5V Tolerant Input (digital pins only)
• On-Chip 2.5V Regulator
• Low-Power, High-Speed CMOS Flash Technology
• C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code.
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT): - Programmable period from 4 ms to 131s
• Single-Supply In-Circuit Serial Programming™ (ICSP™) via Two Pins
• In-Circuit Debug (ICD) with Three Break points via
• Two Pins.

• 10-bit ADC resolution and up to 48 analog inputs
• Flexible and independent ADC trigger sources
• Two comparators with 32 programmable voltage references
• Temperature sensor with ±2ºC accuracy.

• 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline
• Extended instruction set.

• Program memory: 8 Kbyte Flash memory; data retention 20 years at 55 °C after 100 cycles
• RAM: 1 Kbyte
• Data memory: 128 bytes true data EEPROM; endurance up to 100 k write/erase cycles.

NXP S32M2 family is designed for 12 V motor control applications. Based on a system-in-package (SiP) design, it integrates high-voltage analog functionalities (MOSFET gate pre-drivers, physical communication interfaces (LIN/CAN FD), and voltage regulators) with a robust embedded MCU core (S32K Arm® Cortex®-M4/M7 series core), ensuring high-performance and functional safety compliance with ISO 26262 up to ASIL B.

Key features include a platform-based design of motor control edge nodes, enabling faster time-to-market, advanced data analysis capabilities, inverter and motor diagnostic capabilities, and advanced algorithms to minimize in-cabin noise.

Through compatibility with the NXP S32 automotive platform, the S32M2 family enables seamless firmware over-the-air (FOTA) updates, software reuse, and flexibility.

With attention to cost at the system level, S32M2 integrates voltage regulators, pulse width modulators, analog-to-digital converters, timers, and non-volatile memory to reduce overall component count and reduce board space in a 64-pin LQFP-EP package.

The S32M276SFFRD is a reference design board for three-phase BLDC and PMSM motors for automotive motor control applications. It is based on the S32M24x integrated solution that offers a 32-bit Arm Cortex-M4 S32K1 microcontroller and analog die with voltage regulator, gate driver, current sensing, and LIN/CAN physical layer in a system-in-package (SiP) design.

The S32M276SFFRD is designed to offer BOM and PCB size reduction. In a less than 2" diameter (5 cm diameter), the boards can drive BLDC/PMSM motor control applications.

• Only 49 Instructions to Learn: - All single-cycle instructions except branches
• Operating Speed: - DC – 32 MHz oscillator/clock input - DC – 125 ns instruction cycle
• Interrupt Capability with Automatic Context Saving
• 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset
• Direct, Indirect and Relative Addressing modes: - Two full 16-bit File Select Registers (FSRs) - FSRs can read program and data memory.

• Only 35 Instructions to Learn: - All single-cycle instructions except branches
• Operating Speed: - DC – 20 MHz oscillator/clock input - DC – 200 ns instruction cycle
• Interrupt Capability
• 8-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes.

• C Compiler Optimized Architecture
• Only 49 Instructions
• Operating Speed: - DC – 20 MHz clock input - DC – 200 ns instruction cycle
• Interrupt Capability with Automatic Context Saving
• 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset
• Direct, Indirect and Relative Addressing modes: - Two full 16-bit File Select Registers (FSRs) - FSRs can read program and data memory.

The STM32F103xx medium-density performance line family incorporates the high-performance Arm® Cortex®-M3 32-bit RISC core operating at a 72 MHz frequency, high-speed embedded memories (Flash memory up to 128 Kbytes and SRAM up to 20 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer two 12-bit ADCs, three general purpose 16-bit timers plus one PWM timer, as well as standard and advanced communication interfaces: up to two I2Cs and SPIs, three USARTs, an USB and a CAN.

The devices operate from a 2.0 to 3.6 V power supply. They are available in both the –40 to +85°C temperature range and the –40 to +105 °C extended temperature range. A comprehensive set of power-saving mode allows the design of low-power applications.

The STM32F103xx medium-density performance line family includes devices in six different package types: from 36 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.

These features make the STM32F103xx medium-density performance line microcontroller family suitable for a wide range of applications such as motor drives, application control, medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs.